1. Field of the Invention
The present invention relates to a semiconductor package and a method of manufacturing thereof.
2. Description of Related Art
A semiconductor package having a plurality of chips is known. Typically, such a semiconductor package is provided with a package substrate, a first chip, a second chip and a sealing body. The first chip is mounted on a principal surface of the package substrate. The second chip is mounted on a principal surface of the first chip. The first chip and the second chip are sealed by the sealing body. The principal surface of the first chip is a circuit formation surface on which circuits are formed. Specifically, an internal electrode group and an external electrode group are formed on the circuit formation surface. The internal electrode group is used for transmitting/receiving signals to/from the second chip. The internal electrode group of the first chip is in contact with an internal electrode group of the second chip. On the other hand, the external electrode group is electrically connected to an external device. The external electrode group is connected through bonding wires to interconnections formed in the package substrate. The external electrode group is electrically connected to the external device through the package substrate.
In order to protect circuit elements of each chip from electrostatic discharge, the each chip is provided with an electrostatic discharge protection circuit (hereinafter referred to as an ESD protection element). Static electricity tends to affect the chip through electrodes. Therefore, the ESD protection elements are typically provided for both of the external electrode group and the internal electrode group.
It should be noted here that the ESD protection element in this specification is an element having the following function: when a voltage of one end of the ESD protection element exceeds a certain value, an internal circuit of the ESD protection element is turned ON and thereby diverting a current caused by the electrostatic discharge.
By the way, the internal electrode group is not directly connected to the external device. It is considered to be unlikely that static electricity is input from another chip in the semiconductor package through the internal electrode group. It is therefore considered that there is little need to provide the ESD protection element for the internal electrode group.
For example, Japanese Patent Publication JP-2005-223346 (Patent Literature 1) discloses a technique in which an electrostatic breakdown protecting transistor (equivalent to the ESD protection element) is not connected to an input/output terminal (equivalent to the internal electrode group) other than that used for testing and for base substrate.
Besides, a related technique is disclosed in Japanese Patent Publication JP-2005-64362 (Patent Literature 2).
However, the inventors of the present application have recognized the following problem regarding the related technique disclosed in the Patent Literature 1 in which no countermeasure against static electricity is taken with respect to the internal electrode group.
When a semiconductor package is manufactured, chips are first generated. Specifically, a wafer is prepared for generating the chips. Then, circuit elements are formed on the wafer. After that, dicing of the wafer is performed and thereby individual chips are obtained. The obtained chip is mounted on a package substrate. Further, the chip is sealed. After that, electrode balls are attached to the package substrate as necessary and thus a semiconductor package is achieved. When the dicing of the wafer is performed, static electricity is likely to be caused by mechanical contact between the wafer and a dicing equipment. Moreover, during an assembly process between the dicing process and the sealing process, the internal electrode group of the chip is exposed and thus the static electricity can be applied to the internal electrode group. The chip is smaller in size than the wafer and is susceptible to the incident static electricity. Therefore, in the case where no countermeasure against static electricity is taken with respect to the internal electrode group, the electrostatic discharge associated with the internal electrode group may be caused during the assembly process. This electrostatic discharge can destroy circuit elements formed in the chip, which is a problem.
Whereas, in a case where the ESD protection element is provided for the internal electrode group, it is disadvantageous in terms of a chip area. Moreover, signal input/output between chips is performed through the ESD protection element, and thus a voltage level of the input/output signal needs to be made higher. As a result, power consumption is increased, which is a problem.